A phase-locked loop (PLL) is employed in a communication system (e.g., wireless communication system), for example, to generate a carrier frequency for transmission through a transmitter and/or to select a channel frequency of reception at a receiver therein. The PLL may be configured to lock to a desired frequency through adjusting a frequency of an output to match a phase of the output with that of a reference input thereto. Types associated with PLLs include analog PLL, digital PLL, All-Digital PLL (ADPLL) and software PLL.
The ADPLL is a digital architectural solution of a PLL. Advantages of the ADPLL include easy integration with digital base-band, programmability and robustness. The design associated with the ADPLL can be easily migrated to newer process/technology nodes due to the intrinsic digital architecture including a digitally-controlled oscillator (DCO) and a time-to-digital converter (TDC). The DCO does not require an analog control and may be configured to perform frequency control digitally through switching varactors. Fine frequency resolution is achieved through high-speed sigma-delta dithering. The TDC is a part of the phase detector and may include a chain of invertors and flip-flops to perform a fine measurement of a phase difference between the reference clock of the ADPLL and the oscillator output clock.
A low-pass digital filter (e.g., a loop filter) is configured to extract the low-pass portion of the output of an integrator configured to control the DCO. The ADPLL includes a slicer configured to convert a base reference frequency (e.g., from a temperature compensated crystal oscillator (TCXO)) to a frequency associated with the digitized reference clock input to the phase detector. The ADPLL also includes a divider in a feedback path configured to count the oscillator output frequency clock, which is sampled by the reference clock. The sampled count value along with the fractional count value provided by the TDC may be compared with the expected counted value derived from a desired relation between the reference frequency and output frequency to obtain the digital phase error samples.
When there is a near-integer relationship between the output frequency and the reference clock frequency input, the divided frequency components of the output frequency is undesirably coupled to the input of the slicer to cause spur frequency components associated therewith to be manifested at the output of the slicer. The spur frequency components are then coupled to the ADPLL, which, consequently, degrades phase noise and/or the Error Vector Magnitude (EVM) of, for example, a transceiver in which the ADPLL is employed.